Tunable Voltage-Mode Subthreshold CMOS Neuron

Research output: Contribution to book/anthology/report/proceedingArticle in proceedingsResearchpeer-review

To address the ever-increasing computational demands of machine learning applications, neuromorphic computing has emerged as a possible solution. The goal is to design a platform able to mimic the processing strategies of the brain. A neuromorphic system is composed by artificial neurons and synapses implemented in hardware with high level of integration. Such implementations entail challenges including power-efficiency, compactness and biophysical resemblance. This work proposes a new implementation of a neuron circuit, initially introduced by Wijekoon and Dudek. We show that the proposed neuron, designed in a standard 0.18μm CMOS process, consumes 58.5fJ/spike at 0.2V supply voltage. The area covered by the circuit is 16.8% of the area of the state-of-the-art implementation. This result was achieved by lowering the membrane capacitance and the number of transistors. In addition, spiking activity unfolds on a biological time scale-rather than accelerated. The circuit preserves the possibility of being adjusted by external biases to attain different firing patterns.

Original languageEnglish
Title of host publicationProceedings - 2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Number of pages6
Publication year2020
Article number9155044
ISBN (Electronic)9781728157757
Publication statusPublished - 2020
Event2020 IEEE Computer Society Annual Symposium on VLSI - GrandResort, Limassol, Cyprus
Duration: 6 Jul 20208 Jul 2020


Conference2020 IEEE Computer Society Annual Symposium on VLSI

    Research areas

  • CMOS neuron, Izhikevich, Neuromorphic, Spiking neural networks

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