Abstract
Spintronic memories are one of the most promising candidates as a universal memory. Although they offer superior energy efficiency over the conventional memories, benefiting from approximate computing approach, some novel techniques can be applied to lower the power consumption even further. In this brief, we propose a progressive scaling scheme for spin-transfer torque random access memory (STT-RAM) arrays, by which the power consumption is reduced at the expense of small quality degradation. According to the proposed approach, access transistors in STT-RAM cells are scaled based on an optimized scaling factor, where least significant bits and most significant bits come with different bit error rates in the data word. Simulation results show that the proposed approach provides 36.7% write power dissipation and 25% die area savings, respectively, while negligible quality degradation is observed based on mean structural similarity index.
| Original language | English |
|---|---|
| Journal | IEEE Transactions on Circuits and Systems II: Express Briefs |
| Volume | 65 |
| Issue | 7 |
| Pages (from-to) | 938-942 |
| Number of pages | 5 |
| ISSN | 1549-7747 |
| DOIs | |
| Publication status | Published - Jul 2018 |
Keywords
- Degradation
- Energy-Efficiency
- Magnetic tunneling
- Multimedia application
- Multimedia communication
- Random access memory
- STT-RAM
- Streaming media
- Switches
- Transistors
- approximate computing.
- approximate computing
- multimedia application
- energy efficiency