Optimal Layout-Aware CNOT Circuit Synthesis with Qubit Permutation

TY - GEN

T1 - Optimal Layout-Aware CNOT Circuit Synthesis with Qubit Permutation

AU - Shaik, Irfansha

AU - Pol, Jaco van de

N1 - Conference code: 27

PY - 2024/10/16

Y1 - 2024/10/16

N2 - CNOT optimization plays a significant role in noise reduction for Quantum Circuits. Several heuristic and exact approaches exist for CNOT optimization. In this paper, we investigate more complicated variations of optimal synthesis by allowing qubit permutations and handling layout restrictions. We encode such problems into Planning, SAT, and QBF. We provide optimization for both CNOT gate count and circuit depth. For experimental evaluation, we consider standard T-gate optimized benchmarks and optimize CNOT sub-circuits. We show that allowing qubit permutations can further reduce up to 56% in CNOT count and 46% in circuit depth. In the case of optimally mapped circuits under layout restrictions, we observe a reduction up to 17% CNOT count and 19% CNOT depth.

AB - CNOT optimization plays a significant role in noise reduction for Quantum Circuits. Several heuristic and exact approaches exist for CNOT optimization. In this paper, we investigate more complicated variations of optimal synthesis by allowing qubit permutations and handling layout restrictions. We encode such problems into Planning, SAT, and QBF. We provide optimization for both CNOT gate count and circuit depth. For experimental evaluation, we consider standard T-gate optimized benchmarks and optimize CNOT sub-circuits. We show that allowing qubit permutations can further reduce up to 56% in CNOT count and 46% in circuit depth. In the case of optimally mapped circuits under layout restrictions, we observe a reduction up to 17% CNOT count and 19% CNOT depth.

UR - https://www.scopus.com/pages/publications/85216611172

U2 - 10.3233/FAIA240993

DO - 10.3233/FAIA240993

M3 - Article in proceedings

T3 - Frontiers in Artificial Intelligence and Applications

SP - 4207

EP - 4215

BT - ECAI 2024 - 27th European Conference on Artificial Intelligence, 19-24 October 2024, Santiago de Compostela, Spain - Including 13th Conference on Prestigious Applications of Intelligent Systems (PAIS 2024)

A2 - Endriss, Ulle

A2 - Melo, Francisco S.

A2 - Bach, Kerstin

A2 - Bugarin-Diz, Alberto

A2 - Alonso-Moral, Jose M.

A2 - Barro, Senen

A2 - Heintz, Fredrik

PB - IOS Press

T2 - 27th European Conference on Artificial Intelligence

Y2 - 19 October 2024 through 24 October 2024

ER -