NEXUS: A 28nm 3.3pJ/SOP 16-Core Spiking Neural Network with a Diamond Topology for Real-Time Data Processing

TY - JOUR

T1 - NEXUS

T2 - A 28nm 3.3pJ/SOP 16-Core Spiking Neural Network with a Diamond Topology for Real-Time Data Processing

AU - Sadeghi, Maryam

AU - Rezaeiyan, Yasser

AU - Fernández Khatiboun, Darío

AU - Eissa, Sherif

AU - Corradi, Federico

AU - Augustine, Charles

AU - Moradi, Farshad

PY - 2024

Y1 - 2024

N2 - The realization of brain-scale spiking neural networks (SNNs) is impeded by power constraints and low integration density. To address these challenges, multi-core SNNs are utilized to emulate numerous neurons with high energy efficiency, where spike packets are routed through a network-on-chip (NoC). However, the information can be lost in the NoC under high spike traffic conditions, leading to performance degradation. This work presents NEXUS, a 16-core SNN with a diamond-shaped NoC topology fabricated in 28-nm CMOS technology. It integrates 4096 leaky integrate-and-fire (LIF) neurons with 1M 4-bit synaptic weights, occupying an area of 2.16 mm2. The proposed NoC architecture is scalable to any network size, ensuring no data loss due to contending packets with a maximum routing latency of 5.1μs for 16 cores. The proposed congestion management method eliminates the need for FIFO in routers, resulting in a compact router footprint of 0.001 mm2. The proposed neurosynaptic core allows for increasing the processing speed by up to 8.5× depending on input sparsity. The SNN achieves a peak throughput of 4.7 GSOP/s at 0.9 V, consuming a minimum energy per synaptic operation (SOP) of 3.3 pJ at 0.55 V. A 4-layer feed-forward network is mapped onto the chip, classifying MNIST digits with 92.3% accuracy at 8.4Kclassification/ s and consuming 2.7-μJ/classification. Additionally, an audio recognition task mapped onto the chip achieves 87.4% accuracy at 215-μJ/classification.

AB - The realization of brain-scale spiking neural networks (SNNs) is impeded by power constraints and low integration density. To address these challenges, multi-core SNNs are utilized to emulate numerous neurons with high energy efficiency, where spike packets are routed through a network-on-chip (NoC). However, the information can be lost in the NoC under high spike traffic conditions, leading to performance degradation. This work presents NEXUS, a 16-core SNN with a diamond-shaped NoC topology fabricated in 28-nm CMOS technology. It integrates 4096 leaky integrate-and-fire (LIF) neurons with 1M 4-bit synaptic weights, occupying an area of 2.16 mm2. The proposed NoC architecture is scalable to any network size, ensuring no data loss due to contending packets with a maximum routing latency of 5.1μs for 16 cores. The proposed congestion management method eliminates the need for FIFO in routers, resulting in a compact router footprint of 0.001 mm2. The proposed neurosynaptic core allows for increasing the processing speed by up to 8.5× depending on input sparsity. The SNN achieves a peak throughput of 4.7 GSOP/s at 0.9 V, consuming a minimum energy per synaptic operation (SOP) of 3.3 pJ at 0.55 V. A 4-layer feed-forward network is mapped onto the chip, classifying MNIST digits with 92.3% accuracy at 8.4Kclassification/ s and consuming 2.7-μJ/classification. Additionally, an audio recognition task mapped onto the chip achieves 87.4% accuracy at 215-μJ/classification.

KW - Neuromorphic computing

KW - congestion management

KW - network on chip (NoC)

KW - spatio-temporal sparsity

KW - spiking neural network (SNN)

UR - http://www.scopus.com/inward/record.url?scp=85202771322&partnerID=8YFLogxK

U2 - 10.1109/TBCAS.2024.3452635

DO - 10.1109/TBCAS.2024.3452635

M3 - Journal article

C2 - 39213266

SN - 1932-4545

SP - 1

EP - 13

JO - IEEE Transactions on Biomedical Circuits and Systems

JF - IEEE Transactions on Biomedical Circuits and Systems

ER -