Low-Power Pattern Recognition System Using Spintronics Compute-in-memory Architecture

Sonal Shreya; Yasser Rezaeiyan; Maryam Sadeghi; Brajesh Kumar Kaushik; Farshad Moradi

doi:10.1109/NMDC57951.2023.10344005

Low-Power Pattern Recognition System Using Spintronics Compute-in-memory Architecture

Sonal Shreya, Yasser Rezaeiyan, Maryam Sadeghi, Brajesh Kumar Kaushik, Farshad Moradi

Department of Electrical and Computer Engineering - Electronics and Photonics

Research output: Contribution to book/anthology/report/proceeding › Article in proceedings › Research › peer-review

Abstract

Pattern recognition plays an important role in image recognition, classification, and information processing. In this work, energy energy-efficient spintronics-based pattern recognition design using in-memory computing architecture is presented. The paper presents a faster, energy-efficient, and area-efficient pattern recognition approach with three computational steps per pixel recognition process using the training and mean image size. The reduction in critical switching current owing to the voltage-controlled switching mechanism results in a 43% reduction in power consumption as compared to all-spin logic-based design approach for recognizing a 3× 3 pixel image size pattern. This circuitry saves 33% area overhead when compared to conventional compute-in-memory (CiM) architectures based on spin orbit torque. The proposed CiM architectures can further be used for real-time pattern recognition for several applications.

Original language	English
Title of host publication	2023 IEEE Nanotechnology Materials and Devices Conference (NMDC)
Number of pages	5
Publisher	IEEE
Publication date	Dec 2023
Pages	730-734
ISBN (Electronic)	979-8-3503-3546-0, 979-8-3503-3547-7
DOIs	https://doi.org/10.1109/NMDC57951.2023.10344005
Publication status	Published - Dec 2023
Event	IEEE Nanotechnology Materials and Devices Conference (NMDC) - Italy, Paestum Duration: 22 Oct 2023 → 25 Oct 2023 http://10.1109/NMDC57951.2023.10344005

Conference

Conference	IEEE Nanotechnology Materials and Devices Conference (NMDC)
Location	Italy
City	Paestum
Period	22/10/2023 → 25/10/2023
Internet address	http://10.1109/NMDC57951.2023.10344005

Series	IEEE Nanotechnology Materials and Devices Conference (NMDC)
ISSN	2473-0718

Keywords

Computing-in-memory
MRAM
Pattern recognition
Spin-orbit torque
Spintronics devices
Voltage controlled magnetic anisotropy

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10.1109/NMDC57951.2023.10344005

Cite this

@inproceedings{54d1099069a2431d980bad629c346328,

title = "Low-Power Pattern Recognition System Using Spintronics Compute-in-memory Architecture",

abstract = "Pattern recognition plays an important role in image recognition, classification, and information processing. In this work, energy energy-efficient spintronics-based pattern recognition design using in-memory computing architecture is presented. The paper presents a faster, energy-efficient, and area-efficient pattern recognition approach with three computational steps per pixel recognition process using the training and mean image size. The reduction in critical switching current owing to the voltage-controlled switching mechanism results in a 43% reduction in power consumption as compared to all-spin logic-based design approach for recognizing a 3× 3 pixel image size pattern. This circuitry saves 33% area overhead when compared to conventional compute-in-memory (CiM) architectures based on spin orbit torque. The proposed CiM architectures can further be used for real-time pattern recognition for several applications.",

keywords = "Computing-in-memory, MRAM, Pattern recognition, Spin-orbit torque, Spintronics devices, Voltage controlled magnetic anisotropy",

author = "Sonal Shreya and Yasser Rezaeiyan and Maryam Sadeghi and Kaushik, {Brajesh Kumar} and Farshad Moradi",

year = "2023",

month = dec,

doi = "10.1109/NMDC57951.2023.10344005",

language = "English",

series = "IEEE Nanotechnology Materials and Devices Conference (NMDC)",

publisher = "IEEE",

pages = "730--734",

booktitle = "2023 IEEE Nanotechnology Materials and Devices Conference (NMDC)",

note = "IEEE Nanotechnology Materials and Devices Conference (NMDC), NMDC ; Conference date: 22-10-2023 Through 25-10-2023",

url = "http://10.1109/NMDC57951.2023.10344005",

}

Shreya, S , Rezaeiyan, Y , Sadeghi, M, Kaushik, BK & Moradi, F 2023, Low-Power Pattern Recognition System Using Spintronics Compute-in-memory Architecture. in 2023 IEEE Nanotechnology Materials and Devices Conference (NMDC). IEEE, IEEE Nanotechnology Materials and Devices Conference (NMDC), pp. 730-734, IEEE Nanotechnology Materials and Devices Conference (NMDC), Paestum, 22/10/2023. https://doi.org/10.1109/NMDC57951.2023.10344005

Low-Power Pattern Recognition System Using Spintronics Compute-in-memory Architecture. / Shreya, Sonal ; Rezaeiyan, Yasser ; Sadeghi, Maryam et al.
2023 IEEE Nanotechnology Materials and Devices Conference (NMDC). IEEE, 2023. p. 730-734 (IEEE Nanotechnology Materials and Devices Conference (NMDC)).

Research output: Contribution to book/anthology/report/proceeding › Article in proceedings › Research › peer-review

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AU - Shreya, Sonal

AU - Rezaeiyan, Yasser

AU - Sadeghi, Maryam

AU - Kaushik, Brajesh Kumar

AU - Moradi, Farshad

PY - 2023/12

Y1 - 2023/12

N2 - Pattern recognition plays an important role in image recognition, classification, and information processing. In this work, energy energy-efficient spintronics-based pattern recognition design using in-memory computing architecture is presented. The paper presents a faster, energy-efficient, and area-efficient pattern recognition approach with three computational steps per pixel recognition process using the training and mean image size. The reduction in critical switching current owing to the voltage-controlled switching mechanism results in a 43% reduction in power consumption as compared to all-spin logic-based design approach for recognizing a 3× 3 pixel image size pattern. This circuitry saves 33% area overhead when compared to conventional compute-in-memory (CiM) architectures based on spin orbit torque. The proposed CiM architectures can further be used for real-time pattern recognition for several applications.

AB - Pattern recognition plays an important role in image recognition, classification, and information processing. In this work, energy energy-efficient spintronics-based pattern recognition design using in-memory computing architecture is presented. The paper presents a faster, energy-efficient, and area-efficient pattern recognition approach with three computational steps per pixel recognition process using the training and mean image size. The reduction in critical switching current owing to the voltage-controlled switching mechanism results in a 43% reduction in power consumption as compared to all-spin logic-based design approach for recognizing a 3× 3 pixel image size pattern. This circuitry saves 33% area overhead when compared to conventional compute-in-memory (CiM) architectures based on spin orbit torque. The proposed CiM architectures can further be used for real-time pattern recognition for several applications.

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ER -

Low-Power Pattern Recognition System Using Spintronics Compute-in-memory Architecture

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Keywords

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