Domino logic designs for high-performance and leakage-tolerant applications

Farshad Moradi, Tuan Vu Cao, Elena Ioana Vatajelu, Ali Peiravi, Hamid Mahmoodi, Dag Wisland

    Research output: Contribution to journal/Conference contribution in journal/Contribution to newspaperJournal articleResearchpeer-review


    Robustness of high fan-in domino circuits is degraded by technology scaling due to exponential increase in leakage. In this paper, we propose several domino logic circuit techniques to improve the robustness and performance along with leakage power. Lower total power consumption is achieved by utilizing proposed techniques. According to the simulations in TSMC 65 nm CMOS process, the proposed circuits increase noise immunity for wide OR gates by at least 3.5X and shows performance improvement of up to 20% compared to conventional domino logic circuits. For FinFET simulation TCAD tools have been used.
    Original languageEnglish
    Pages (from-to)247–254
    Number of pages8
    Publication statusPublished - Jun 2013


    • Domino logic, CMOS, Leakage


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