Department of Business Development and Technology

Binary-Quintuple Progression Based 12-Switch 25-Level Converter with Nearest Level Modulation Technique for Grid-Tied and Standalone Applications

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  • Nidhi Mishra, Indian Institute of Technology, Delhi
  • ,
  • Shivam Kumar Yadav, Indian Institute of Technology, Delhi
  • ,
  • Bhim Singh, Indian Institute of Technology, Delhi
  • ,
  • Sanjeevikumar Padmanaban
  • Frede Blaabjerg, Aalborg University

This article introduces a cascaded packed U cell (CPUC) multilevel converter (MLC) to achieve a higher-level count in converter voltage with a minimum number of switches. Here, two five-level packed U cell topologies are connected in a cascaded manner to obtain 25 levels in its output converter voltage. The switch count in CPUC is reduced to 12, as compared to the number of semiconductor devices used for obtaining 25 levels in converter output. A binary-quintuple progression is used for selection of voltage ratios between dc voltage sources and capacitors. CPUC is operated at low-frequency switching, using the nearest level modulation technique. The fundamental switching frequency ensures reduced switching losses as compared to pulsewidth modulation schemes. The converter performance is analyzed for grid-tied and standalone applications. The performance parameters such as total harmonic distortion (THD) of converter voltage and THD of grid/load current are examined. The CPUC configuration is modeled and simulated in MATLAB/Simulink, and test results are taken using OPAL-RT test bench. The acquired simulation and test results confirm viability, practicability, acceptability, and cost-effectiveness of CPUC-MLI converter over existing MLC topologies for efficient power conversion.

Original languageEnglish
Article number9275358
JournalIEEE Transactions on Industry Applications
Pages (from-to)3214-3223
Number of pages10
Publication statusPublished - 1 May 2021
Externally publishedYes

Bibliographical note

Funding Information:
Manuscript received February 15, 2020; revised August 18, 2020 and October 5, 2020; accepted November 23, 2020. Date of publication December 1, 2020; date of current version May 19, 2021. Paper 2020-MCRE-0295.R2, approved for publication in the IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS. This work was supported in part by the Department of Science and Technology (DST) under FIST scheme under Grant RP03195, in part by the OPAL-RT under Grant RP03253, in part by Joint UK-India Clean Energy (JUICE) under Grant RP03391, in part by Indo-US Project under Grant RP03443, in part by SERI under Grant RP03357, and in part by J.C. Bose Fellowship under Grant RP03128. (Corresponding Author: Nidhi Mishra.) Nidhi Mishra, Shivam Kumar Yadav, and Bhim Singh are with the Department of Electrical Engineering, Indian Institute of Technology Delhi, New Delhi 110016, India (e-mail:;;

Publisher Copyright:
© 1972-2012 IEEE.

    Research areas

  • Cascaded packed U cell (CPUC), nearest level modulation, photovoltaic array, power quality

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