Advanced Acceleration and Implementation of Convolutional Neural Networks on FPGAs

TY - GEN

T1 - Advanced Acceleration and Implementation of Convolutional Neural Networks on FPGAs

AU - Jensen, Mikkel

AU - Toft Jacobsen, Jesper

AU - Sharifirad, Iman

AU - Boudjadar, Jalil

N1 - Conference code: 25

PY - 2023

Y1 - 2023

N2 - In recent years, embedded platforms became attractive targets to deploy machine learning (ML) -empowered control and processing systems. However, securing a high performance executability to satisfy the hard real-time constraints of such systems on resource-limited platforms, such as FPGAs, is a challenging task. This paper introduces a methodology for deploying hardware-accelerated, adaptable convolutional neural networks (CNN) on embedded FPGA platforms. It enables automated synthesis of hardware IPs, instantiation of CNN architectures and mapping of the CNN layers processing to hardware IPs. This will result in iteration-free deployment reducing the expensive cost of HW synthesis, so that the acceleration hardware IPs are synthesized once and configured at runtime following the CNN architecture. To demonstrate the applicability and assess the performance of our deployment model, we implemented and deployed a segment-based acceleration of a image classification CNN on Xilinx ZYBO Z7 FPGA board. Among others, we have analyzed the computation performance, accuracy and trade-offs between CNN size, image segmentation size, resources utilization and scalability.

AB - In recent years, embedded platforms became attractive targets to deploy machine learning (ML) -empowered control and processing systems. However, securing a high performance executability to satisfy the hard real-time constraints of such systems on resource-limited platforms, such as FPGAs, is a challenging task. This paper introduces a methodology for deploying hardware-accelerated, adaptable convolutional neural networks (CNN) on embedded FPGA platforms. It enables automated synthesis of hardware IPs, instantiation of CNN architectures and mapping of the CNN layers processing to hardware IPs. This will result in iteration-free deployment reducing the expensive cost of HW synthesis, so that the acceleration hardware IPs are synthesized once and configured at runtime following the CNN architecture. To demonstrate the applicability and assess the performance of our deployment model, we implemented and deployed a segment-based acceleration of a image classification CNN on Xilinx ZYBO Z7 FPGA board. Among others, we have analyzed the computation performance, accuracy and trade-offs between CNN size, image segmentation size, resources utilization and scalability.

KW - Acceleration

KW - Adaptive Architectures

KW - Convolutional Neural Networks

KW - FPGAs

KW - Hardware synthesis

UR - http://www.scopus.com/inward/record.url?scp=85189858273&partnerID=8YFLogxK

U2 - 10.1109/HPCC-DSS-SmartCity-DependSys60770.2023.00082

DO - 10.1109/HPCC-DSS-SmartCity-DependSys60770.2023.00082

M3 - Article in proceedings

SN - 979-8-3503-3002-1

SP - 558

EP - 565

BT - 2023 IEEE International Conference on High Performance Computing & Communications, Data Science & Systems, Smart City & Dependability in Sensor, Cloud & Big Data Systems & Application (HPCC/DSS/SmartCity/DependSys)

A2 - Chen, Jinjun

A2 - Yang, Laurence T.

PB - IEEE

T2 - IEEE International Conference on High Performance Computing and Communications

Y2 - 13 December 2023 through 15 December 2023

ER -