A Novel Nondestructive Bit-Line Discharging Scheme for Deep Submicrometer STT-RAM

Behzad Zeinali; Jens Kargaard Madsen; Praveen Raghavan; Farshad Moradi

A Novel Nondestructive Bit-Line Discharging Scheme for Deep Submicrometer STT-RAM

Behzad Zeinali, Jens Kargaard Madsen, Praveen Raghavan, Farshad Moradi

Research output: Contribution to conference › Paper › Research › peer-review

Abstract

A combination of semiconductor integrated circuits
(IC) and a dense array of scaled magnetic tunnel junctions (MTJ)
makes promising Spin-Transfer Torque Random Access Memory
(STT-RAM). This emerging memory minimizes the leakage power consumption and provides a high density at scaled technologies. In this paper, we propose a novel non-destructive self-reference sensing scheme for STT-RAM. The proposed technique overcomes the large bit-to-bit variation of MTJ resistance. In the proposed scheme, the stored value in the STTRAM cell preserves, hence, the long write-back operation is eliminated. Besides, the sensing scheme is accomplished in one step. In this scheme, the Bit-Line is pre-charged and then discharged during read operation. The MTJ resistance state can be found by comparing the time constant of discharging. The simulation results show the overall sensing time is 4 ns when the Bit-Line capacitance is equal to 200 fF.

Original language	English
Publication date	2016
Number of pages	5
Publication status	Published - 2016
Event	The 34th IEEE International Conference on Computer Design - Phoenix, Arizona, Phoenix, United States Duration: 3 Oct 2016 → 5 Oct 2016 Conference number: 34

Conference

Conference	The 34th IEEE International Conference on Computer Design
Number	34
Location	Phoenix, Arizona
Country/Territory	United States
City	Phoenix
Period	03/10/2016 → 05/10/2016

Keywords

STT-RAM
Self-reference sense scheme
FinFET

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Cite this

@conference{1f7a0509cb804392b29d0424dacc4871,

title = "A Novel Nondestructive Bit-Line Discharging Scheme for Deep Submicrometer STT-RAM",

abstract = "A combination of semiconductor integrated circuits(IC) and a dense array of scaled magnetic tunnel junctions (MTJ)makes promising Spin-Transfer Torque Random Access Memory(STT-RAM). This emerging memory minimizes the leakage power consumption and provides a high density at scaled technologies. In this paper, we propose a novel non-destructive self-reference sensing scheme for STT-RAM. The proposed technique overcomes the large bit-to-bit variation of MTJ resistance. In the proposed scheme, the stored value in the STTRAM cell preserves, hence, the long write-back operation is eliminated. Besides, the sensing scheme is accomplished in one step. In this scheme, the Bit-Line is pre-charged and then discharged during read operation. The MTJ resistance state can be found by comparing the time constant of discharging. The simulation results show the overall sensing time is 4 ns when the Bit-Line capacitance is equal to 200 fF.",

keywords = "STT-RAM, Self-reference sense scheme, FinFET",

author = "Behzad Zeinali and Madsen, {Jens Kargaard} and Praveen Raghavan and Farshad Moradi",

year = "2016",

language = "English",

note = "The 34th IEEE International Conference on Computer Design, ICCD 2016 ; Conference date: 03-10-2016 Through 05-10-2016",

}

TY - CONF

T1 - A Novel Nondestructive Bit-Line Discharging Scheme for Deep Submicrometer STT-RAM

AU - Zeinali, Behzad

AU - Madsen, Jens Kargaard

AU - Raghavan, Praveen

AU - Moradi, Farshad

N1 - Conference code: 34

PY - 2016

Y1 - 2016

N2 - A combination of semiconductor integrated circuits(IC) and a dense array of scaled magnetic tunnel junctions (MTJ)makes promising Spin-Transfer Torque Random Access Memory(STT-RAM). This emerging memory minimizes the leakage power consumption and provides a high density at scaled technologies. In this paper, we propose a novel non-destructive self-reference sensing scheme for STT-RAM. The proposed technique overcomes the large bit-to-bit variation of MTJ resistance. In the proposed scheme, the stored value in the STTRAM cell preserves, hence, the long write-back operation is eliminated. Besides, the sensing scheme is accomplished in one step. In this scheme, the Bit-Line is pre-charged and then discharged during read operation. The MTJ resistance state can be found by comparing the time constant of discharging. The simulation results show the overall sensing time is 4 ns when the Bit-Line capacitance is equal to 200 fF.

AB - A combination of semiconductor integrated circuits(IC) and a dense array of scaled magnetic tunnel junctions (MTJ)makes promising Spin-Transfer Torque Random Access Memory(STT-RAM). This emerging memory minimizes the leakage power consumption and provides a high density at scaled technologies. In this paper, we propose a novel non-destructive self-reference sensing scheme for STT-RAM. The proposed technique overcomes the large bit-to-bit variation of MTJ resistance. In the proposed scheme, the stored value in the STTRAM cell preserves, hence, the long write-back operation is eliminated. Besides, the sensing scheme is accomplished in one step. In this scheme, the Bit-Line is pre-charged and then discharged during read operation. The MTJ resistance state can be found by comparing the time constant of discharging. The simulation results show the overall sensing time is 4 ns when the Bit-Line capacitance is equal to 200 fF.

KW - STT-RAM

KW - Self-reference sense scheme

KW - FinFET

M3 - Paper

T2 - The 34th IEEE International Conference on Computer Design

Y2 - 3 October 2016 through 5 October 2016

ER -

A Novel Nondestructive Bit-Line Discharging Scheme for Deep Submicrometer STT-RAM

Abstract

Conference

Keywords

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