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A low power and soft error resilience guard-gated Quartro-based flip-flop in 45 nm CMOS technology

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A low power and soft error resilience guard-gated Quartro-based flip-flop in 45 nm CMOS technology. / Kumar, Sabavat Satheesh; Sundaram, Kumaravel; Padmanaban, Sanjeevikumar; Holm-Nielsen, Jens Bo; Blaabjerg, Frede.

In: IET Circuits, Devices and Systems, Vol. 15, No. 6, 09.2021, p. 571-580.

Research output: Contribution to journal/Conference contribution in journal/Contribution to newspaperJournal articleResearchpeer-review

Harvard

Kumar, SS, Sundaram, K, Padmanaban, S, Holm-Nielsen, JB & Blaabjerg, F 2021, 'A low power and soft error resilience guard-gated Quartro-based flip-flop in 45 nm CMOS technology', IET Circuits, Devices and Systems, vol. 15, no. 6, pp. 571-580. https://doi.org/10.1049/cds2.12052

APA

Kumar, S. S., Sundaram, K., Padmanaban, S., Holm-Nielsen, J. B., & Blaabjerg, F. (2021). A low power and soft error resilience guard-gated Quartro-based flip-flop in 45 nm CMOS technology. IET Circuits, Devices and Systems, 15(6), 571-580. https://doi.org/10.1049/cds2.12052

CBE

Kumar SS, Sundaram K, Padmanaban S, Holm-Nielsen JB, Blaabjerg F. 2021. A low power and soft error resilience guard-gated Quartro-based flip-flop in 45 nm CMOS technology. IET Circuits, Devices and Systems. 15(6):571-580. https://doi.org/10.1049/cds2.12052

MLA

Kumar, Sabavat Satheesh et al. "A low power and soft error resilience guard-gated Quartro-based flip-flop in 45 nm CMOS technology". IET Circuits, Devices and Systems. 2021, 15(6). 571-580. https://doi.org/10.1049/cds2.12052

Vancouver

Kumar SS, Sundaram K, Padmanaban S, Holm-Nielsen JB, Blaabjerg F. A low power and soft error resilience guard-gated Quartro-based flip-flop in 45 nm CMOS technology. IET Circuits, Devices and Systems. 2021 Sep;15(6):571-580. https://doi.org/10.1049/cds2.12052

Author

Kumar, Sabavat Satheesh ; Sundaram, Kumaravel ; Padmanaban, Sanjeevikumar ; Holm-Nielsen, Jens Bo ; Blaabjerg, Frede. / A low power and soft error resilience guard-gated Quartro-based flip-flop in 45 nm CMOS technology. In: IET Circuits, Devices and Systems. 2021 ; Vol. 15, No. 6. pp. 571-580.

Bibtex

@article{3f3caf2613c84ce7ae6ac0ab18230f7b,
title = "A low power and soft error resilience guard-gated Quartro-based flip-flop in 45 nm CMOS technology",
abstract = "Conventional flip-flops are more vulnerable to particle strikes in a radiation environment. To overcome this disadvantage, in the literature, many radiation-hardened flip-flops (FFs) based on techniques like triple modular redundancy, dual interlocked cell, Quatro and guard-gated Quatro cell, and so on, are discussed. The flip-flop realized using radiation hardened by design Quatro cell is named as the improved version of Quatro flip-flop (IVQFF). Single event upset (SEU) at inverter stages of master/slave and at output are the two drawbacks of IVQFF. This study proposes a guard-gated Quatro FF (GQFF) using guard-gated Quatro cell and Muller C-element. To overcome the SEU at inverter stages of IVQFF, in GQFF, the inverter stages are realized in a parallel fashion. A dual-input Muller C-element is connected to the GQFF output stage to mask the SEU and thus maintain the correct output. The proposed GQFF tolerates both single node upset (SNU) and double node upset (DNU). It also achieves low power. To prove the efficacy, GQFF and the existing FFs are implemented in 45 nm Complementary Metal Oxide Semiconductor (CMOS) technology. From the simulation results, it may be noted that the GQFF is 100% immune to SNUs and 50% immune to DNUs.",
author = "Kumar, {Sabavat Satheesh} and Kumaravel Sundaram and Sanjeevikumar Padmanaban and Holm-Nielsen, {Jens Bo} and Frede Blaabjerg",
note = "Publisher Copyright: {\textcopyright} 2021 The Authors. IET Circuits, Devices & Systems published by John Wiley & Sons Ltd on behalf of The Institution of Engineering and Technology. Copyright: Copyright 2021 Elsevier B.V., All rights reserved.",
year = "2021",
month = sep,
doi = "10.1049/cds2.12052",
language = "English",
volume = "15",
pages = "571--580",
journal = "IET Circuits, Devices and Systems",
issn = "1751-858X",
publisher = "John Wiley & Sons Inc.",
number = "6",

}

RIS

TY - JOUR

T1 - A low power and soft error resilience guard-gated Quartro-based flip-flop in 45 nm CMOS technology

AU - Kumar, Sabavat Satheesh

AU - Sundaram, Kumaravel

AU - Padmanaban, Sanjeevikumar

AU - Holm-Nielsen, Jens Bo

AU - Blaabjerg, Frede

N1 - Publisher Copyright: © 2021 The Authors. IET Circuits, Devices & Systems published by John Wiley & Sons Ltd on behalf of The Institution of Engineering and Technology. Copyright: Copyright 2021 Elsevier B.V., All rights reserved.

PY - 2021/9

Y1 - 2021/9

N2 - Conventional flip-flops are more vulnerable to particle strikes in a radiation environment. To overcome this disadvantage, in the literature, many radiation-hardened flip-flops (FFs) based on techniques like triple modular redundancy, dual interlocked cell, Quatro and guard-gated Quatro cell, and so on, are discussed. The flip-flop realized using radiation hardened by design Quatro cell is named as the improved version of Quatro flip-flop (IVQFF). Single event upset (SEU) at inverter stages of master/slave and at output are the two drawbacks of IVQFF. This study proposes a guard-gated Quatro FF (GQFF) using guard-gated Quatro cell and Muller C-element. To overcome the SEU at inverter stages of IVQFF, in GQFF, the inverter stages are realized in a parallel fashion. A dual-input Muller C-element is connected to the GQFF output stage to mask the SEU and thus maintain the correct output. The proposed GQFF tolerates both single node upset (SNU) and double node upset (DNU). It also achieves low power. To prove the efficacy, GQFF and the existing FFs are implemented in 45 nm Complementary Metal Oxide Semiconductor (CMOS) technology. From the simulation results, it may be noted that the GQFF is 100% immune to SNUs and 50% immune to DNUs.

AB - Conventional flip-flops are more vulnerable to particle strikes in a radiation environment. To overcome this disadvantage, in the literature, many radiation-hardened flip-flops (FFs) based on techniques like triple modular redundancy, dual interlocked cell, Quatro and guard-gated Quatro cell, and so on, are discussed. The flip-flop realized using radiation hardened by design Quatro cell is named as the improved version of Quatro flip-flop (IVQFF). Single event upset (SEU) at inverter stages of master/slave and at output are the two drawbacks of IVQFF. This study proposes a guard-gated Quatro FF (GQFF) using guard-gated Quatro cell and Muller C-element. To overcome the SEU at inverter stages of IVQFF, in GQFF, the inverter stages are realized in a parallel fashion. A dual-input Muller C-element is connected to the GQFF output stage to mask the SEU and thus maintain the correct output. The proposed GQFF tolerates both single node upset (SNU) and double node upset (DNU). It also achieves low power. To prove the efficacy, GQFF and the existing FFs are implemented in 45 nm Complementary Metal Oxide Semiconductor (CMOS) technology. From the simulation results, it may be noted that the GQFF is 100% immune to SNUs and 50% immune to DNUs.

UR - http://www.scopus.com/inward/record.url?scp=85102650121&partnerID=8YFLogxK

U2 - 10.1049/cds2.12052

DO - 10.1049/cds2.12052

M3 - Journal article

AN - SCOPUS:85102650121

VL - 15

SP - 571

EP - 580

JO - IET Circuits, Devices and Systems

JF - IET Circuits, Devices and Systems

SN - 1751-858X

IS - 6

ER -