TY - GEN
T1 - A Hybrid Spin-CMOS Flash ADC based on Spin Hall Effect and Spin Transfer Torque
AU - Ghanatian Najafabadi, Hamdam
AU - Farkhani, Hooman
AU - Moradi, Farshad
N1 - Publisher Copyright:
© 2022 IEEE.
PY - 2022/10
Y1 - 2022/10
N2 - In this paper, a 3-bit hybrid spin-CMOS Flash analog to digital converter (ADC) is developed, which works based on switching of perpendicular-anisotropy magnetic tunnel junctions (p-MTJs) using both spin Hall effect (SHE) and spin-transfer torque (STT). The structure consists of unconnected p-MTJs in which heavy metals (HMs) are implemented with different cross-sectional areas leading to devices with different critical current (IC) values. IC values act as reference currents (Iref) eliminating the need for transistors with different sizes creating various values of Iref. Moreover, the power-hungry comparators in complementary metal-oxide-semiconductor (CMOS) Flash ADC can be replaced with p-MTJs because they compare the input current (Iin) with their IC. Hence, this approach can reduce the chip area and the mismatch issue as compared to the conventional CMOS Flash ADC. In this structure, a copy of Iin passes through the HM of each p-MTJ, which improves the tunnel magnetoresistance (TMR) and as a results increasing the reading reliability, linearity, and speed of spin Hall-based ADCs with attached HMs. The simulation results in 180nm CMOS technology show 845 μW of power consumption at 200 MS/s with the differential nonlinearity (DNL) and integral nonlinearity (INL) of -0.149 LSB (least significant bit) and 0.085 LSB, respectively.
AB - In this paper, a 3-bit hybrid spin-CMOS Flash analog to digital converter (ADC) is developed, which works based on switching of perpendicular-anisotropy magnetic tunnel junctions (p-MTJs) using both spin Hall effect (SHE) and spin-transfer torque (STT). The structure consists of unconnected p-MTJs in which heavy metals (HMs) are implemented with different cross-sectional areas leading to devices with different critical current (IC) values. IC values act as reference currents (Iref) eliminating the need for transistors with different sizes creating various values of Iref. Moreover, the power-hungry comparators in complementary metal-oxide-semiconductor (CMOS) Flash ADC can be replaced with p-MTJs because they compare the input current (Iin) with their IC. Hence, this approach can reduce the chip area and the mismatch issue as compared to the conventional CMOS Flash ADC. In this structure, a copy of Iin passes through the HM of each p-MTJ, which improves the tunnel magnetoresistance (TMR) and as a results increasing the reading reliability, linearity, and speed of spin Hall-based ADCs with attached HMs. The simulation results in 180nm CMOS technology show 845 μW of power consumption at 200 MS/s with the differential nonlinearity (DNL) and integral nonlinearity (INL) of -0.149 LSB (least significant bit) and 0.085 LSB, respectively.
KW - Flash ADC
KW - magnetic tunnel junction (MTJ)
KW - spin-Hall effect (SHE)
KW - spin-transfer torque (STT)
UR - http://www.scopus.com/inward/record.url?scp=85145879507&partnerID=8YFLogxK
U2 - 10.1109/ICCD56317.2022.00107
DO - 10.1109/ICCD56317.2022.00107
M3 - Article in proceedings
T3 - Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors
SP - 701
EP - 704
BT - Proceedings - 2022 IEEE 40th International Conference on Computer Design, ICCD 2022
PB - IEEE
T2 - 40th IEEE International Conference on Computer Design, ICCD 2022
Y2 - 23 October 2022 through 26 October 2022
ER -