8T-SRAM Cell with Improved Read and Write Margins in 65 nm CMOS Technology

Farshad Moradi; Mohammad Tohidi; Behzad Zeinali; Jens Kargaard Madsen

doi:10.1007/978-3-319-25279-7_6

8T-SRAM Cell with Improved Read and Write Margins in 65 nm CMOS Technology

Farshad Moradi, Mohammad Tohidi, Behzad Zeinali, Jens Kargaard Madsen

Research output: Contribution to book/anthology/report/proceeding › Book chapter › Research › peer-review

7 Citations (Scopus)

Original language	English
Title of host publication	VLSI-SoC: Internet of Things Foundations : 22nd IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2014, Playa del Carmen, Mexico, October 6–8, 2014, Revised and Extended Selected Papers
Editors	Luc Claesen, Maria-Teresa Sanz-Pascual, Ricardo Reis, Arturo Sarmiento-Reyes
Number of pages	14
Volume	464
Publisher	Springer
Publication date	2015
Pages	95-109
ISBN (Print)	978-3-319-25278-0
ISBN (Electronic)	978-3-319-25279-7
DOIs	https://doi.org/10.1007/978-3-319-25279-7_6
Publication status	Published - 2015
Event	IFIP/IEEE International Conference on Very Large Scale Integration - Playa del Carmen, Mexico Duration: 6 Oct 2014 → 8 Oct 2014 Conference number: 22nd

Conference

Conference	IFIP/IEEE International Conference on Very Large Scale Integration
Number	22nd
Country/Territory	Mexico
City	Playa del Carmen
Period	06/10/2014 → 08/10/2014

Series	IFIP AICT - Advances in Information and Communication technology
Volume	464
ISSN	1868-4238

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10.1007/978-3-319-25279-7_6

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Moradi, F., Tohidi, M., Zeinali, B., & Madsen, J. K. (2015). 8T-SRAM Cell with Improved Read and Write Margins in 65 nm CMOS Technology. In L. Claesen, M.-T. Sanz-Pascual, R. Reis, & A. Sarmiento-Reyes (Eds.), VLSI-SoC: Internet of Things Foundations: 22nd IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2014, Playa del Carmen, Mexico, October 6–8, 2014, Revised and Extended Selected Papers (Vol. 464, pp. 95-109). Springer. https://doi.org/10.1007/978-3-319-25279-7_6

Moradi, Farshad ; Tohidi, Mohammad ; Zeinali, Behzad et al. / 8T-SRAM Cell with Improved Read and Write Margins in 65 nm CMOS Technology. VLSI-SoC: Internet of Things Foundations: 22nd IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2014, Playa del Carmen, Mexico, October 6–8, 2014, Revised and Extended Selected Papers. editor / Luc Claesen ; Maria-Teresa Sanz-Pascual ; Ricardo Reis ; Arturo Sarmiento-Reyes. Vol. 464 Springer, 2015. pp. 95-109 (IFIP AICT - Advances in Information and Communication technology, Vol. 464).

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author = "Farshad Moradi and Mohammad Tohidi and Behzad Zeinali and Madsen, {Jens Kargaard}",

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Moradi, F, Tohidi, M, Zeinali, B & Madsen, JK 2015, 8T-SRAM Cell with Improved Read and Write Margins in 65 nm CMOS Technology. in L Claesen, M-T Sanz-Pascual, R Reis & A Sarmiento-Reyes (eds), VLSI-SoC: Internet of Things Foundations: 22nd IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2014, Playa del Carmen, Mexico, October 6–8, 2014, Revised and Extended Selected Papers. vol. 464, Springer, IFIP AICT - Advances in Information and Communication technology, vol. 464, pp. 95-109, IFIP/IEEE International Conference on Very Large Scale Integration , Playa del Carmen, Mexico, 06/10/2014. https://doi.org/10.1007/978-3-319-25279-7_6

8T-SRAM Cell with Improved Read and Write Margins in 65 nm CMOS Technology. / Moradi, Farshad; Tohidi, Mohammad; Zeinali, Behzad et al.
VLSI-SoC: Internet of Things Foundations: 22nd IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2014, Playa del Carmen, Mexico, October 6–8, 2014, Revised and Extended Selected Papers. ed. / Luc Claesen; Maria-Teresa Sanz-Pascual; Ricardo Reis; Arturo Sarmiento-Reyes. Vol. 464 Springer, 2015. p. 95-109 (IFIP AICT - Advances in Information and Communication technology, Vol. 464).

Research output: Contribution to book/anthology/report/proceeding › Book chapter › Research › peer-review

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T1 - 8T-SRAM Cell with Improved Read and Write Margins in 65 nm CMOS Technology

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AU - Zeinali, Behzad

AU - Madsen, Jens Kargaard

N1 - Conference code: 22nd

PY - 2015

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U2 - 10.1007/978-3-319-25279-7_6

DO - 10.1007/978-3-319-25279-7_6

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A2 - Sanz-Pascual, Maria-Teresa

A2 - Reis, Ricardo

A2 - Sarmiento-Reyes, Arturo

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T2 - IFIP/IEEE International Conference on Very Large Scale Integration

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Moradi F, Tohidi M, Zeinali B, Madsen JK. 8T-SRAM Cell with Improved Read and Write Margins in 65 nm CMOS Technology. In Claesen L, Sanz-Pascual MT, Reis R, Sarmiento-Reyes A, editors, VLSI-SoC: Internet of Things Foundations: 22nd IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2014, Playa del Carmen, Mexico, October 6–8, 2014, Revised and Extended Selected Papers. Vol. 464. Springer. 2015. p. 95-109. (IFIP AICT - Advances in Information and Communication technology, Vol. 464). doi: 10.1007/978-3-319-25279-7_6