Novel Circuit for In-Memory Computing within STT-RAM Memory Blocks

TY - GEN

T1 - Novel Circuit for In-Memory Computing within STT-RAM Memory Blocks

AU - Shafaghi, Pegah

AU - Rezaeiyan, Yasser

AU - Shreya, Sonal

AU - Moradi, Farshad

AU - Farkhani, Hooman

PY - 2024/10/29

Y1 - 2024/10/29

N2 - While the von Neumann architectures involve separate processing and memory units, the movement of data between them results in considerable time and energy expenses. One promising alternative is in-memory computing, where data is processed within the memory itself. Historically, one of the primary methods to store data has been based on the presence or absence of charge, as seen in DRAM, SRAM, etc. However, a novel class of memory devices is emerging, known as resistive memories, which store data by changing the orientations of ferromagnetic magnetization, resulting in changes in its resistance. Amongst them, Spin Transfer Torque RAM (STTRAM) is one of the most promising resistive memories due to its unique features such as CMOS compatibility, scalability, and nonvolatility. This paper introduces a novel circuit designed to implement OR/NOR and AND/NAND logic functions within STT-RAM memory bit cells, enabling in-memory computing (IMC). Importantly, the proposed circuit can be integrated into existing STT-RAM memory blocks without necessitating any structural modifications. The proposed circuit has significantly fewer devices and consumes less energy compared to the best state-of-the-art designs while its speed is comparable with theirs. The correct operation of the proposed logic circuit in the presence of process variations has been confirmed using Monte Carlo simulations in 65-nm CMOS technology.

AB - While the von Neumann architectures involve separate processing and memory units, the movement of data between them results in considerable time and energy expenses. One promising alternative is in-memory computing, where data is processed within the memory itself. Historically, one of the primary methods to store data has been based on the presence or absence of charge, as seen in DRAM, SRAM, etc. However, a novel class of memory devices is emerging, known as resistive memories, which store data by changing the orientations of ferromagnetic magnetization, resulting in changes in its resistance. Amongst them, Spin Transfer Torque RAM (STTRAM) is one of the most promising resistive memories due to its unique features such as CMOS compatibility, scalability, and nonvolatility. This paper introduces a novel circuit designed to implement OR/NOR and AND/NAND logic functions within STT-RAM memory bit cells, enabling in-memory computing (IMC). Importantly, the proposed circuit can be integrated into existing STT-RAM memory blocks without necessitating any structural modifications. The proposed circuit has significantly fewer devices and consumes less energy compared to the best state-of-the-art designs while its speed is comparable with theirs. The correct operation of the proposed logic circuit in the presence of process variations has been confirmed using Monte Carlo simulations in 65-nm CMOS technology.

KW - In-memory computing

KW - STT-RAM

KW - Tunnel Magnetoresistance (TMR)

KW - spintronics

UR - http://www.scopus.com/inward/record.url?scp=85211906386&partnerID=8YFLogxK

U2 - 10.1109/NorCAS64408.2024.10752464

DO - 10.1109/NorCAS64408.2024.10752464

M3 - Article in proceedings

BT - 2024 IEEE Nordic Circuits and Systems Conference (NorCAS)

A2 - Nurmi, Jari

A2 - Rodrigues, Joachim

A2 - Pezzarossa, Luca

A2 - Aberg, Viktor

A2 - Behmanesh, Baktash

T2 - IEEE Nordic Circuits and Systems Conference (NorCAS)

Y2 - 29 October 2024 through 30 October 2024

ER -