Input Offset Estimation of CMOS Integrated Circuits in Weak Inversion

TY - JOUR

T1 - Input Offset Estimation of CMOS Integrated Circuits in Weak Inversion

AU - Akbari, Meysam

AU - Hashemipour, Omid

AU - Moradi, Farshad

PY - 2018/9

Y1 - 2018/9

N2 - This brief studies the current mismatch of MOS transistors operating in weak inversion region. Explicit formulas are derived from the drain-current relationship of a long-channel MOS transistor. By referring the drain-current variance to the gate terminal under the small-signal conditions, the dependence of the gate-source voltage on the design parameters and sources of mismatch can be considered. This will help designers to choose the optimum sizes and the efficient gm/I D ratio for current offset reduction of transistors that their mismatch affects the circuit performance, significantly. In order to confirm the accuracy of the calculated drain-current variance, the hand analysis results are compared with MATLAB simulator outputs. In addition, the input offset of a conventional folded-cascode amplifier is estimated by hand analysis, and the results are compared with SPICE simulator outputs through Monte Carlo analysis.

AB - This brief studies the current mismatch of MOS transistors operating in weak inversion region. Explicit formulas are derived from the drain-current relationship of a long-channel MOS transistor. By referring the drain-current variance to the gate terminal under the small-signal conditions, the dependence of the gate-source voltage on the design parameters and sources of mismatch can be considered. This will help designers to choose the optimum sizes and the efficient gm/I D ratio for current offset reduction of transistors that their mismatch affects the circuit performance, significantly. In order to confirm the accuracy of the calculated drain-current variance, the hand analysis results are compared with MATLAB simulator outputs. In addition, the input offset of a conventional folded-cascode amplifier is estimated by hand analysis, and the results are compared with SPICE simulator outputs through Monte Carlo analysis.

KW - Current variance

KW - MOS transistor

KW - mismatch

KW - weak inversion

U2 - 10.1109/TVLSI.2018.2830749

DO - 10.1109/TVLSI.2018.2830749

M3 - Journal article

SN - 1063-8210

VL - 26

SP - 1812

EP - 1816

JO - I E E E Transactions on Very Large Scale Integration (VLSI) Systems

JF - I E E E Transactions on Very Large Scale Integration (VLSI) Systems

IS - 9

M1 - 8362694

ER -