With the extension of Moore’s law and Dennard scaling, transistors confront the slowing rate of performance gain from shrinking nodes. The integrated circuits will be restrained by inadequate device density, energy consuming and computing speed, especially for the emergence of Internet of things, big data and brain-like computing. Memristor, the fourth basic circuit element, has been examined the promising alternative for addressing the issues, owing to superior non-volatile storage, analog simulation and large-scale integration. Among the flourishing memrsitors, the working principle, mechanism and physiochemical property vary greatly. It is essential to dive into basic resistive switching mechanism for the development of advanced memristor.
In this thesis, memristive properties are investigated from three aspects: surficial modification, the co-designed geometry and atomic localization of conductive filaments. Starting from basic geometry, the channel regulation and contact engineering are investigated for the preparation of high-quality devices. The implementation of co-designed graphene sensor contributes to the finding of intriguing resistive behavior in non-destructive way. For the shrink of memristive domain, the anions based resistive switching behavior is also discovered within sub-nanometer lamellar structure, which is promising for the implementation of low-consumption device. Companying the dimensional scaling from bulk metal oxides to 2D materials, in situ CAFM and KPFM measurements are conducted to unveil the correlation of work function change and memristive evolution.
In view of multiple factors on exploring electrical properties of memristor, this thesis summarizes our attempts on various systems ranging from dimensional change to physicochemical regulation with the goal of laying a solid foundation for cut-edging devices.