Hardware Implementation of a Resource-Efficient Router for Multi-Core Spiking Neural Networks

Maryam Sadeghi; Yasser Rezaeiyan; Darío Fernández Khatiboun; Farshad Moradi

doi:10.1109/ISCAS46773.2023.10182040

Hardware Implementation of a Resource-Efficient Router for Multi-Core Spiking Neural Networks

Maryam Sadeghi, Yasser Rezaeiyan, Darío Fernández Khatiboun, Farshad Moradi

Institut for Elektro- og Computerteknologi - Electronics and Photonics

Publikation: Bidrag til bog/antologi/rapport/proceeding › Konferencebidrag i proceedings › Forskning › peer review

1 Citationer (Scopus)

Abstract

Spiking neural networks (SNNs) are envisioned to be a better alternative to artificial neural networks (ANNs) for targeted applications. Multi-core implementation of SNNs has been built to achieve a resource-efficient design. However, managing the spike traffic congestion while routing the spikes between different cores requires a performance-resource tradeoff to avoid any packet loss. This paper presents a novel router architecture servicing ongoing packets in a 2-D mesh network while guaranteeing no packet drop. Here, the packets are distributed across different paths to reduce spike traffic. The proposed router suitable for a 16 × 16 network occupies an area of 0.001mm2 in 28nm CMOS technology, while consuming 75 fJ/transmission.

Originalsprog	Engelsk
Titel	ISCAS 2023 - 56th IEEE International Symposium on Circuits and Systems, Proceedings
Forlag	IEEE
Publikationsdato	2023
Sider	1-5
ISBN (Trykt)	978-1-6654-5109-3
ISBN (Elektronisk)	9781665451093
DOI	https://doi.org/10.1109/ISCAS46773.2023.10182040
Status	Udgivet - 2023
Begivenhed	IEEE International Symposium on Circuits and Systems - Monterey, USA Varighed: 21 maj 2023 → 25 maj 2023

Konference

Konference	IEEE International Symposium on Circuits and Systems
Land/Område	USA
By	Monterey
Periode	21/05/2023 → 25/05/2023

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Citationsformater

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title = "Hardware Implementation of a Resource-Efficient Router for Multi-Core Spiking Neural Networks",

abstract = "Spiking neural networks (SNNs) are envisioned to be a better alternative to artificial neural networks (ANNs) for targeted applications. Multi-core implementation of SNNs has been built to achieve a resource-efficient design. However, managing the spike traffic congestion while routing the spikes between different cores requires a performance-resource tradeoff to avoid any packet loss. This paper presents a novel router architecture servicing ongoing packets in a 2-D mesh network while guaranteeing no packet drop. Here, the packets are distributed across different paths to reduce spike traffic. The proposed router suitable for a 16 × 16 network occupies an area of 0.001mm2 in 28nm CMOS technology, while consuming 75 fJ/transmission.",

keywords = "Brain-inspired computing, artificial neural network, neuromorphic computing, spiking neural network",

author = "Maryam Sadeghi and Yasser Rezaeiyan and {Fern{\'a}ndez Khatiboun}, Dar{\'i}o and Farshad Moradi",

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publisher = "IEEE",

note = "IEEE International Symposium on Circuits and Systems ; Conference date: 21-05-2023 Through 25-05-2023",

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Sadeghi, M, Rezaeiyan, Y , Fernández Khatiboun, D & Moradi, F 2023, Hardware Implementation of a Resource-Efficient Router for Multi-Core Spiking Neural Networks. i ISCAS 2023 - 56th IEEE International Symposium on Circuits and Systems, Proceedings. IEEE, s. 1-5, IEEE International Symposium on Circuits and Systems, Monterey, California, USA, 21/05/2023. https://doi.org/10.1109/ISCAS46773.2023.10182040

Hardware Implementation of a Resource-Efficient Router for Multi-Core Spiking Neural Networks. / Sadeghi, Maryam; Rezaeiyan, Yasser ; Fernández Khatiboun, Darío et al.
ISCAS 2023 - 56th IEEE International Symposium on Circuits and Systems, Proceedings. IEEE, 2023. s. 1-5.

Publikation: Bidrag til bog/antologi/rapport/proceeding › Konferencebidrag i proceedings › Forskning › peer review

TY - GEN

T1 - Hardware Implementation of a Resource-Efficient Router for Multi-Core Spiking Neural Networks

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AB - Spiking neural networks (SNNs) are envisioned to be a better alternative to artificial neural networks (ANNs) for targeted applications. Multi-core implementation of SNNs has been built to achieve a resource-efficient design. However, managing the spike traffic congestion while routing the spikes between different cores requires a performance-resource tradeoff to avoid any packet loss. This paper presents a novel router architecture servicing ongoing packets in a 2-D mesh network while guaranteeing no packet drop. Here, the packets are distributed across different paths to reduce spike traffic. The proposed router suitable for a 16 × 16 network occupies an area of 0.001mm2 in 28nm CMOS technology, while consuming 75 fJ/transmission.

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Hardware Implementation of a Resource-Efficient Router for Multi-Core Spiking Neural Networks

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