Flexible Energy-Efficient Implementation of Adaptive Spiking Encoder for Neuromorphic Processors

TY - GEN

T1 - Flexible Energy-Efficient Implementation of Adaptive Spiking Encoder for Neuromorphic Processors

AU - Zamani, Milad

AU - Ronchini, Margherita

AU - Huynh, Hai Au

AU - Farkhani, Hooman

AU - Moradi, Farshad

PY - 2021

Y1 - 2021

N2 - Neuromorphic computing could pave the way to a new generation of smart sensors that can process signals locally through Spiking Neural Networks (SNNs). For this paradigm to take hold, it is necessary to have an analog-to-spike encoder adaptable to a wide range of applications. The encoding system should offer the possibility to try different encoding algorithms, giving freedom to the designers to select the most appropriate approach for the target task. At the same time, it should feature a tunable parameter to modulate the spike density, in the pursuit of a compromise between accuracy and power consumption. Therefore, the goal of this work is to provide a platform enabling the conversion of analog signals to a sequence of spikes, characterized by flexibility, high energy efficiency, and small area. We introduce an encoder designed and simulated in a standard 0.18 μm CMOS process which benefits from a switch-capacitor and a dynamic comparator to achieve very high energy efficiency. The controller unit can switch between Slope-based or Step-Forward Encoding algorithms. The encoder consumes 30 fJ/spike at 1.5 V supply voltage and occupies an area of 0.00325

AB - Neuromorphic computing could pave the way to a new generation of smart sensors that can process signals locally through Spiking Neural Networks (SNNs). For this paradigm to take hold, it is necessary to have an analog-to-spike encoder adaptable to a wide range of applications. The encoding system should offer the possibility to try different encoding algorithms, giving freedom to the designers to select the most appropriate approach for the target task. At the same time, it should feature a tunable parameter to modulate the spike density, in the pursuit of a compromise between accuracy and power consumption. Therefore, the goal of this work is to provide a platform enabling the conversion of analog signals to a sequence of spikes, characterized by flexibility, high energy efficiency, and small area. We introduce an encoder designed and simulated in a standard 0.18 μm CMOS process which benefits from a switch-capacitor and a dynamic comparator to achieve very high energy efficiency. The controller unit can switch between Slope-based or Step-Forward Encoding algorithms. The encoder consumes 30 fJ/spike at 1.5 V supply voltage and occupies an area of 0.00325

KW - Neuromorphic

KW - Signal-to-spike

KW - Slope-based encoding

KW - Spiking neural networks

KW - Step-forward encoding

UR - http://www.scopus.com/inward/record.url?scp=85109016443&partnerID=8YFLogxK

U2 - 10.1109/ISCAS51556.2021.9401103

DO - 10.1109/ISCAS51556.2021.9401103

M3 - Article in proceedings

AN - SCOPUS:85109016443

BT - 2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings

PB - IEEE

T2 - 53rd IEEE International Symposium on Circuits and Systems, ISCAS 2021

Y2 - 22 May 2021 through 28 May 2021

ER -