Digital Hardware Implementation of ReSuMe Learning Algorithm for Spiking Neural Networks

Darío Fernández Khatiboun; Yasser Rezaeiyan; Margherita Ronchini; Maryam Sadeghi; Milad Zamani; Farshad Moradi

doi:10.1109/EMBC40787.2023.10340282

Digital Hardware Implementation of ReSuMe Learning Algorithm for Spiking Neural Networks

Darío Fernández Khatiboun, Yasser Rezaeiyan, Margherita Ronchini, Maryam Sadeghi, Milad Zamani, Farshad Moradi

Institut for Elektro- og Computerteknologi - Electronics and Photonics

Publikation: Bidrag til bog/antologi/rapport/proceeding › Konferencebidrag i proceedings › Forskning › peer review

1 Citationer (Scopus)

Abstract

Within this paper, we demonstrate the feasibility of the FPGA implementation as well as the 180nm CMOS circuit design of a particular biologically plausible supervised learning algorithm (ReSuMe). Based on the Spike-Timing-Dependent Plasticity (STDP) learning phenomenon, this design proposes a fully configurable implementation of STDP learning window function to adjust the learning process for different applications, optimizing results for each use case. The CMOS implementation in 180nm technology node supplied with 1.8V shows a core area of 0.78mm2 and verifies the suitability of an on-chip ReSuMe learning algorithm implementation and its capability of integration with a multitude of external and already designed structures of Spiking Neural Networks (SNNs).

Originalsprog	Engelsk
Titel	2023 45th Annual International Conference of the IEEE Engineering in Medicine & Biology Society (EMBC)
Forlag	IEEE
Publikationsdato	jul. 2023
ISBN (Elektronisk)	979-8-3503-2448-8, 979-8-3503-2447-1
DOI	https://doi.org/10.1109/EMBC40787.2023.10340282
Status	Udgivet - jul. 2023

Navn	I E E E Engineering in Medicine and Biology Society. Conference Proceedings
ISSN	2375-7477

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10.1109/EMBC40787.2023.10340282

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@inproceedings{a8ce957392d540c2ba3fcc5a8ecb0cca,

title = "Digital Hardware Implementation of ReSuMe Learning Algorithm for Spiking Neural Networks",

abstract = "Within this paper, we demonstrate the feasibility of the FPGA implementation as well as the 180nm CMOS circuit design of a particular biologically plausible supervised learning algorithm (ReSuMe). Based on the Spike-Timing-Dependent Plasticity (STDP) learning phenomenon, this design proposes a fully configurable implementation of STDP learning window function to adjust the learning process for different applications, optimizing results for each use case. The CMOS implementation in 180nm technology node supplied with 1.8V shows a core area of 0.78mm2 and verifies the suitability of an on-chip ReSuMe learning algorithm implementation and its capability of integration with a multitude of external and already designed structures of Spiking Neural Networks (SNNs).",

author = "{Fern{\'a}ndez Khatiboun}, Dar{\'i}o and Yasser Rezaeiyan and Margherita Ronchini and Maryam Sadeghi and Milad Zamani and Farshad Moradi",

year = "2023",

month = jul,

doi = "10.1109/EMBC40787.2023.10340282",

language = "English",

series = "I E E E Engineering in Medicine and Biology Society. Conference Proceedings",

publisher = "IEEE",

booktitle = "2023 45th Annual International Conference of the IEEE Engineering in Medicine & Biology Society (EMBC)",

}

Fernández Khatiboun, D , Rezaeiyan, Y , Ronchini, M , Sadeghi, M , Zamani, M & Moradi, F 2023, Digital Hardware Implementation of ReSuMe Learning Algorithm for Spiking Neural Networks. i 2023 45th Annual International Conference of the IEEE Engineering in Medicine & Biology Society (EMBC). IEEE, I E E E Engineering in Medicine and Biology Society. Conference Proceedings. https://doi.org/10.1109/EMBC40787.2023.10340282

Digital Hardware Implementation of ReSuMe Learning Algorithm for Spiking Neural Networks. / Fernández Khatiboun, Darío ; Rezaeiyan, Yasser ; Ronchini, Margherita et al.
2023 45th Annual International Conference of the IEEE Engineering in Medicine & Biology Society (EMBC). IEEE, 2023. (I E E E Engineering in Medicine and Biology Society. Conference Proceedings).

Publikation: Bidrag til bog/antologi/rapport/proceeding › Konferencebidrag i proceedings › Forskning › peer review

TY - GEN

T1 - Digital Hardware Implementation of ReSuMe Learning Algorithm for Spiking Neural Networks

AU - Fernández Khatiboun, Darío

AU - Rezaeiyan, Yasser

AU - Ronchini, Margherita

AU - Sadeghi, Maryam

AU - Zamani, Milad

AU - Moradi, Farshad

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AB - Within this paper, we demonstrate the feasibility of the FPGA implementation as well as the 180nm CMOS circuit design of a particular biologically plausible supervised learning algorithm (ReSuMe). Based on the Spike-Timing-Dependent Plasticity (STDP) learning phenomenon, this design proposes a fully configurable implementation of STDP learning window function to adjust the learning process for different applications, optimizing results for each use case. The CMOS implementation in 180nm technology node supplied with 1.8V shows a core area of 0.78mm2 and verifies the suitability of an on-chip ReSuMe learning algorithm implementation and its capability of integration with a multitude of external and already designed structures of Spiking Neural Networks (SNNs).

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M3 - Article in proceedings

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T3 - I E E E Engineering in Medicine and Biology Society. Conference Proceedings

BT - 2023 45th Annual International Conference of the IEEE Engineering in Medicine & Biology Society (EMBC)

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Fernández Khatiboun D , Rezaeiyan Y , Ronchini M , Sadeghi M , Zamani M , Moradi F. Digital Hardware Implementation of ReSuMe Learning Algorithm for Spiking Neural Networks. I 2023 45th Annual International Conference of the IEEE Engineering in Medicine & Biology Society (EMBC). IEEE. 2023. (I E E E Engineering in Medicine and Biology Society. Conference Proceedings). doi: 10.1109/EMBC40787.2023.10340282

Digital Hardware Implementation of ReSuMe Learning Algorithm for Spiking Neural Networks

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