TY - JOUR
T1 - CMOS Front End for Interfacing Spin-Hall Nano-Oscillators for Neuromorphic Computing in the GHz Range
AU - Fiorelli, Rafaella
AU - Peralías, Eduardo
AU - Méndez-Romero, Roberto
AU - Rajabali, Mona
AU - Kumar, Akash
AU - Zahedinejad, Mohammad
AU - Åkerman, Johan
AU - Moradi, Farshad
AU - Serrano-Gotarredona, Teresa
AU - Linares-Barranco, Bernabé
PY - 2023/1
Y1 - 2023/1
N2 - Spin-Hall-effect nano-oscillators are promising beyond the CMOS devices currently available, and can potentially be used to emulate the functioning of neurons in computational neuromorphic systems. As they oscillate in the 4–20 GHz range, they could potentially be used for building highly accelerated neural hardware platforms. However, due to their extremely low signal level and high impedance at their output, as well as their microwave-range operating frequency, discerning whether the SHNO is oscillating or not carries a great challenge when its state read-out circuit is implemented using CMOS technologies. This paper presents the first CMOS front-end read-out circuitry, implemented in 180 nm, working at a SHNO oscillation frequency up to 4.7 GHz, managing to discern SHNO amplitudes of 100 µV even for an impedance as large as 300 Ω and a noise figure of 5.3 dB300 Ω. A design flow of this front end is presented, as well as the architecture of each of its blocks. The study of the low-noise amplifier is deepened for its intrinsic difficulties in the design, satisfying the characteristics of SHNOs.
AB - Spin-Hall-effect nano-oscillators are promising beyond the CMOS devices currently available, and can potentially be used to emulate the functioning of neurons in computational neuromorphic systems. As they oscillate in the 4–20 GHz range, they could potentially be used for building highly accelerated neural hardware platforms. However, due to their extremely low signal level and high impedance at their output, as well as their microwave-range operating frequency, discerning whether the SHNO is oscillating or not carries a great challenge when its state read-out circuit is implemented using CMOS technologies. This paper presents the first CMOS front-end read-out circuitry, implemented in 180 nm, working at a SHNO oscillation frequency up to 4.7 GHz, managing to discern SHNO amplitudes of 100 µV even for an impedance as large as 300 Ω and a noise figure of 5.3 dB300 Ω. A design flow of this front end is presented, as well as the architecture of each of its blocks. The study of the low-noise amplifier is deepened for its intrinsic difficulties in the design, satisfying the characteristics of SHNOs.
KW - CMOS
KW - frond-end
KW - LNA
KW - mixer
KW - neuromorphic
KW - RF
KW - SHNO
KW - spin-hall oscillators
UR - http://www.scopus.com/inward/record.url?scp=85145886024&partnerID=8YFLogxK
U2 - 10.3390/electronics12010230
DO - 10.3390/electronics12010230
M3 - Journal article
AN - SCOPUS:85145886024
SN - 2079-9292
VL - 12
JO - Electronics
JF - Electronics
IS - 1
M1 - 230
ER -