TY - JOUR
T1 - A Low-Power Fast Tag Comparator by Modifying Charging Scheme of Wide Fan-in Dynamic OR gates
AU - Nasserian, Mahshid
AU - Kafi-Kangi, Mohammad
AU - Maymandi Nejad, Mohammad
AU - Moradi, Farshad
PY - 2016/1/1
Y1 - 2016/1/1
N2 - In this paper, a new charging scheme for reducing the power consumption of dynamic circuits is presented. The proposed technique is suitable for large fan-in gates where the dynamic node discharges frequently. Simulation results demonstrate that the proposed method is efficiently controlling the internal voltage swing and hence decreasing the power consumption of the wide fan-in OR gate without sacrificing other circuit parameters such as gate speed, area or noise immunity. The power-delay product of a simulated 8-input OR gate is reduced by 46%, compared to its conventional dynamic counterpart in the 90 nm CMOS technology. Another important benefit of the proposed approach is 99X reduction in power dissipation of the gate load by limiting its switching activity. Furthermore, the delay of the proposed circuit experiences only 0.94% variation over 10% fluctuation in the threshold voltages of all transistors for a 32-bit OR gate. Using the proposed technique, a 40-bit tag comparator is simulated at 1 GHz clock frequency. The power consumption of the designed circuit is as low as 1.987 μW/MHz, while the delay and unity noise gain (UNG) of the circuit are 244 ps and 499 mV, respectively.
AB - In this paper, a new charging scheme for reducing the power consumption of dynamic circuits is presented. The proposed technique is suitable for large fan-in gates where the dynamic node discharges frequently. Simulation results demonstrate that the proposed method is efficiently controlling the internal voltage swing and hence decreasing the power consumption of the wide fan-in OR gate without sacrificing other circuit parameters such as gate speed, area or noise immunity. The power-delay product of a simulated 8-input OR gate is reduced by 46%, compared to its conventional dynamic counterpart in the 90 nm CMOS technology. Another important benefit of the proposed approach is 99X reduction in power dissipation of the gate load by limiting its switching activity. Furthermore, the delay of the proposed circuit experiences only 0.94% variation over 10% fluctuation in the threshold voltages of all transistors for a 32-bit OR gate. Using the proposed technique, a 40-bit tag comparator is simulated at 1 GHz clock frequency. The power consumption of the designed circuit is as low as 1.987 μW/MHz, while the delay and unity noise gain (UNG) of the circuit are 244 ps and 499 mV, respectively.
KW - dynamic logic, power-delay product, Low power, wide fan-in
UR - http://www.scopus.com/inward/record.url?scp=84949793799&partnerID=8YFLogxK
U2 - 10.1016/j.vlsi.2015.09.004
DO - 10.1016/j.vlsi.2015.09.004
M3 - Journal article
SN - 0167-9260
VL - 52
SP - 129
EP - 141
JO - Integration
JF - Integration
IS - January
ER -