Abstract
In this paper, a low-power electroencephalogram (EEG) analog front-end (AFE) with ultra-high input impedance is presented. This AFE can be utilized for both dry and non-contact biomedical applications due to its very high input impedance along with DC signal suppression. The amplifier achieves an input impedance of 45 F 1 T and a common mode rejection ratio (CMRR) higher than 110 dB. The power consumption of the proposed 8-channel AFE and its input referred noise over the 0.5-100 Hz bandwidth are 1.62 μW and 2.62 μV rms, respectively. This yields a noise efficiency factor (NEF) of 3.11. The simulations are carried out in the 180 nm standard CMOS technology using a ± 0.5 V power supply.
Originalsprog | Engelsk |
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Titel | 2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016 : VLSI-SoC |
Antal sider | 6 |
Vol/bind | 2016 |
Forlag | IEEE Press |
Publikationsdato | 22 nov. 2016 |
Artikelnummer | 7753539 |
ISBN (Elektronisk) | 978-1-5090-3561-8 |
DOI | |
Status | Udgivet - 22 nov. 2016 |
Begivenhed | 2016 IFIP/IEEE International Conference on Very Large Scale Integration - Tallinn, Estland Varighed: 26 sep. 2016 → 28 sep. 2016 |
Konference
Konference | 2016 IFIP/IEEE International Conference on Very Large Scale Integration |
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Land/Område | Estland |
By | Tallinn |
Periode | 26/09/2016 → 28/09/2016 |