A 1-GHz charge pump PLL frequency synthesizer for IEEE 1394b PHY

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  • J. Ji, University of Electronic Science and Technology of China, China
  • H. Liu, Integrated Device Technology, Shanghai, China
  • Q. Li, Denmark
This paper presents an implementation of multi-rate SerDes transceiver for IEEE 1394b applications. Simple and effective pre-emphasis and equalizer circuits are used at transmitter and receiver, respectively. A phase interpolator based clock and data recovery circuit with optimized linearity is also described. With an on-chip fully integrated phase locked loop, the transceiver works at data rates of 100Mb/s, 400Mb/s and 800Mb/s, supporting three different operating modes of S100b, S400b and S800b for IEEE 1394b. The chip has been fabricated using 0.13μm technology. The die area of transceiver is 2.9*1.6 mm including bonding pads and the total power dissipation is 284 mW with 1.2V and 3.3V supply voltages. © 2012 IEEE.
Original languageEnglish
JournalJournal of Electronic Science and Technology
Pages (from-to)319-326
Number of pages8
Publication statusPublished - Dec 2012

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