Schedulability and Memory Interference Analysis of Multicore Preemptive Real-time Systems

Publikation: Forskning - peer reviewKonferenceabstrakt til konference

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Schedulability and Memory Interference Analysis of Multicore Preemptive Real-time Systems. / Boudjadar, Jalil; Nadjm-Tehrani, Simin.

2017. Abstract fra the 8th ACM/SPEC International Conference on Performance Engineering, L'Aquila, Italien.

Publikation: Forskning - peer reviewKonferenceabstrakt til konference

Harvard

APA

Boudjadar, J., & Nadjm-Tehrani, S. (2017). Schedulability and Memory Interference Analysis of Multicore Preemptive Real-time Systems. Abstract fra the 8th ACM/SPEC International Conference on Performance Engineering, L'Aquila, Italien.DOI: 10.1145/3030207.3030233

CBE

Boudjadar J, Nadjm-Tehrani S. 2017. Schedulability and Memory Interference Analysis of Multicore Preemptive Real-time Systems. Abstract fra the 8th ACM/SPEC International Conference on Performance Engineering, L'Aquila, Italien. Tilgængelig fra: 10.1145/3030207.3030233

MLA

Vancouver

Boudjadar J, Nadjm-Tehrani S. Schedulability and Memory Interference Analysis of Multicore Preemptive Real-time Systems. 2017. Abstract fra the 8th ACM/SPEC International Conference on Performance Engineering, L'Aquila, Italien. Tilgængelig fra, DOI: 10.1145/3030207.3030233

Author

Boudjadar, Jalil ; Nadjm-Tehrani, Simin. / Schedulability and Memory Interference Analysis of Multicore Preemptive Real-time Systems. Abstract fra the 8th ACM/SPEC International Conference on Performance Engineering, L'Aquila, Italien.12 s.

Bibtex

@conference{389b92281e9249ddb958abc4f29118a4,
title = "Schedulability and Memory Interference Analysis of Multicore Preemptive Real-time Systems",
abstract = "Today’s embedded systems demand increasing computingpower to accommodate the ever-growing software functionality.Automotive and avionic systems aim to leverage thehigh performance capabilities of multicore platforms, but arefaced with challenges with respect to temporal predictability.Multicore designers have achieved much progress onimprovement of memory-dependent performance in cachingsystems and shared memories in general. However, havingapplications running simultaneously and requesting the accessto the shared memories concurrently leads to interference.The performance unpredictability resulting from interferenceat any shared memory level may lead to violationof the timing properties in safety-critical real-time systems.In this paper, we introduce a formal analysis framework forthe schedulability and memory interference of multicore systemswith shared caches and DRAM. We build a multicoresystem model with a fine grained application behavior givenin terms of periodic preemptible tasks, described with explicitread and write access numbers for shared caches andDRAM. We also provide a method to analyze and recommendcandidates for task-to-core reallocation with the goalto find schedulable configurations if a given system is notschedulable. Our model-based framework is realized usingUppaal and has been used to analyze a case study.",
keywords = "Schedulability, memory interference, processor utilization, multicore systems, task migration, model checking",
author = "Jalil Boudjadar and Simin Nadjm-Tehrani",
year = "2017",
month = "4",
doi = "10.1145/3030207.3030233",

}

RIS

TY - ABST

T1 - Schedulability and Memory Interference Analysis of Multicore Preemptive Real-time Systems

AU - Boudjadar,Jalil

AU - Nadjm-Tehrani,Simin

PY - 2017/4

Y1 - 2017/4

N2 - Today’s embedded systems demand increasing computingpower to accommodate the ever-growing software functionality.Automotive and avionic systems aim to leverage thehigh performance capabilities of multicore platforms, but arefaced with challenges with respect to temporal predictability.Multicore designers have achieved much progress onimprovement of memory-dependent performance in cachingsystems and shared memories in general. However, havingapplications running simultaneously and requesting the accessto the shared memories concurrently leads to interference.The performance unpredictability resulting from interferenceat any shared memory level may lead to violationof the timing properties in safety-critical real-time systems.In this paper, we introduce a formal analysis framework forthe schedulability and memory interference of multicore systemswith shared caches and DRAM. We build a multicoresystem model with a fine grained application behavior givenin terms of periodic preemptible tasks, described with explicitread and write access numbers for shared caches andDRAM. We also provide a method to analyze and recommendcandidates for task-to-core reallocation with the goalto find schedulable configurations if a given system is notschedulable. Our model-based framework is realized usingUppaal and has been used to analyze a case study.

AB - Today’s embedded systems demand increasing computingpower to accommodate the ever-growing software functionality.Automotive and avionic systems aim to leverage thehigh performance capabilities of multicore platforms, but arefaced with challenges with respect to temporal predictability.Multicore designers have achieved much progress onimprovement of memory-dependent performance in cachingsystems and shared memories in general. However, havingapplications running simultaneously and requesting the accessto the shared memories concurrently leads to interference.The performance unpredictability resulting from interferenceat any shared memory level may lead to violationof the timing properties in safety-critical real-time systems.In this paper, we introduce a formal analysis framework forthe schedulability and memory interference of multicore systemswith shared caches and DRAM. We build a multicoresystem model with a fine grained application behavior givenin terms of periodic preemptible tasks, described with explicitread and write access numbers for shared caches andDRAM. We also provide a method to analyze and recommendcandidates for task-to-core reallocation with the goalto find schedulable configurations if a given system is notschedulable. Our model-based framework is realized usingUppaal and has been used to analyze a case study.

KW - Schedulability, memory interference, processor utilization, multicore systems, task migration, model checking

U2 - 10.1145/3030207.3030233

DO - 10.1145/3030207.3030233

M3 - Conference abstract for conference

ER -