Behzad Zeinali


Behzad Zeinali


Project title
Low Voltage/Low power design in future nodes (FinFET and nanowire based devices)  

Main supervisor: Farshad Moradi

Co-supervisor(s): Jens Kargaard Madsen – Praveen Raghavan (IMEC)                 

Project period: 01/05/2014 to 30/04/2017


Project description
The past few decades have seen the evolution of semiconductor industry driven by technology scaling. Miniaturization of bulk Field Effect Transistors (FETs) along with scaling of power supply voltage has provided the benefits of higher performance, lower power, and larger integration density. However, future scaling will face considerable challenges, e.g. short-channel effects (SCEs) causing the design and optimization of circuits becomes very challenging.

One approach to counter these effects is to introduce alternate device which possess inherently better robustness to SCEs in comparison to existing technology. Among these alternatives, multiple-gate FETs such as FinFETs or gate wrap-around FETs are emerging as promising candidates. FinFETs have potential for analog applications as well as improving the performance of digital circuits such as static random access memories (SRAM) which are widely used in most of digital and computer systems. In this respect, Intel will use the 3-D trigate transistors commercially in 22-nm technology node and so a strong interest has emerged among semiconductor industries in forming 14 and 10-nm bulk FinFET.

In this project, FinFET devices utilize for SRAM modules in both circuit and device level designs. Besides, we will investigate FinFET and their potentials for low-power applications and design some analog and mixed-signal building block by FinFET in sub 14-nm technologies using the Design Kits provided by IMEC.   

External partners/project that the PhD is part of
In this project, IMEC will be actively involved to host our research on FinFET technology 6 months per year.


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